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Imec and Synopsys Collaborate on 3D Stacked IC Development
Synopsys Galaxy Custom Designer Accelerates Analog/Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction
Synopsys System Studio Speeds DSP Algorithm Development With New Matrix Data-Type Support
Synopsys Posts Financial Results for First Quarter Fiscal Year 2010
Great article on managing complex....
Janick Bergeron
“What might be in store for India?”
Karen Bartleson
An Interview with Eric Huang
Rick Jamison
Synopsys USB 3.0 Finalist for EDN....
Eric Huang
The Hitchhiker’s Guide to ESL – Part 2....
Frank Schirrmeister
You can have any colour as long as it....
Navraj Nandra
MAR
22
ISQED 2010
San Jose, CA
MAR
23
SmartDRD Custom Layout Automation
Webinar
MAR
24
In-Design Rail Analysis for Design Closure
Webinar
MAR
25
Verify AMS Circuits with CustomSim
Webinar
MAR
29
SNUG San Jose
Santa Clara, CA
MAR
31
Complementing Emulation
Webinar
APR
07
Improving Your Design Productivity Using GCA
Webinar
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The Big Design Squeeze: How to get faster design turns in FPGA-based designs
In-Design for Faster Design Closure
3-D TCAD Simulation with Sentaurus
Reducing Design Margins Using PrimeTime Advanced OCV
DesignWare IP for AMBA 3 AXI On-Chip Bus
Transaction-level Debug Using VCS
DesignWare IP for HDMI
Compliant to 1.4 spec including HEAC, 3D formats, 4K resolution and more
New! DFTMAX Video
Higher compression for pin-limited test methodologies
PrimeTime Multicore
Enables designers to take full advantage of multicore performance.
StarRC Custom Extraction
Fast, high-accuracy extraction to accelerate custom AMS/digital design
HAPS-A31
Stratix III Rapid Prototyping and Algorithm Acceleration Board
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