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A View from the Top
I had an epiphany while reading Eric Carle stories to my three year old daughter. And boy is she is smart! She figured out for me at her young age already the power of marketing in positioning high technology.
Frank Schirrmeister
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Observations and views from 3 of Synopsys’ top AMS/custom design technologists.
Fred Sendig, Kishore Singhal, Bob Lefferts
Verification Martial Arts
In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances.
Janick Bergeron
The Standards Game
Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson
All Synopsys Blogs
HSPICE SIG VIDEOLOG
HSPICE: Tackling Design Integrity of Multi-Gbps Systems
HSPICE TIPS WEBINAR
Reduce simulation time without compromising HSPICE gold-standard accuracy
CUSTOMEXPLORER ULTRA WEBINAR
Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
CUSTOMSIM WEBINAR
Extending Digital Verification Techniques to Mixed-Signal Designs
News
LG Electronics Accelerates Analog Simulation by 10X with Synopsys CustomSim
Synopsys HSPICE Simulator Delivers 6X Faster Throughput for Intrinsity's....
Synopsys Discovery AMS Enables Analog Bits to Achieve 45nm SERDES Verification
Synopsys and TSMC Collaborate on Advanced HSPICE Modeling Technology for 40-nm....
Synopsys Launches HSPICE Integrator Program With 25 Founding Members
Synopsys HSPICE Simulator Accelerates ARM's 45-Nanometer Physical IP Development
Synopsys HSPICE Simulator and SISoft Deliver Signal Integrity Analysis Solution
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All Synopsys News
Articles
Migrating Complex Networking ASIC Verification Environment
How VHDL designers can exploit SystemVerilog
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
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Blogs
A View from the Top
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Verification Martial Arts
The Standards Game
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White Papers
Utilizing Digital Techniques for Analog and Mixed-Signal Verification
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Webinars
Galaxy Custom Designer--A Complete Custom Implementation Flow
Robust SI Analysis of a DDR2 Interface with HSPICE
Predicting PLL Phase Noise & Jitter with HSPICE RF
Nov.7 Archived Webcast HSIMplus – Beyond FAST Spice Simulation – Listen Now!
Faster Verification Performance with VCS Native Testbench and RVM
Static Verification with LEDA in Discovery Verification Platform
Introduction to SystemVerilog
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DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
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