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Ensuring that complex SoCs meet manufacturing test requirements is a significant challenge. The Synopsys synthesis-based test solution maximizes productivity, providing designers, DFT engineers and product engineers with the fastest and most cost-effective path to high-quality manufacturing tests and high-volume silicon. Synthesis-based technology minimizes the impact test logic has on design timing, area, power and congestion. This eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. The Synopsys test solution is comprised of DFTMAX compression and TetraMAX ATPG for power-aware scan test, DesignWare STAR Memory System for test and repair of embedded memories, DesignWare IP for self-test of high-speed SERDES interfaces, and Yield Explorer for design-centric yield analysis.
| | Complete Interface IP Solutions for the Most Popular Protocols |
- Fully integrated flow from DFT to ATPG, and from diagnostics to yield analysis.
- Shortens design cycle, increases productivity and provides highest timing and area correlation with physical results.
- Decreases manufacturing costs by significantly reducing both test application time and test data volume.
- High compression on pin-limited designs, down to a single scan channel.
- Implementation and verification of IEEE 1149.1 boundary scan design.
- Broad support for at-speed testing and advance fault models ensures ultra-high test quality.
- Power-aware testing maintains high test quality and reduces yield loss on low power designs.
- Scalable embedded memory testing, repair and debug with interactive silicon debug.
- Integrated logic and memory test for faster design closure, smaller area overhead.
- Faster design convergence with automatic congestion optimization using DC Graphical.
- Design-centric yield analysis quickly finds the root cause of silicon defects.
- Direct interface between ATPG and yield analysis ensures high data throughput for volume diagnostics.
- Self-test of DesignWare SERDES IP for fast debug of high-speed interfaces.
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