Design Compiler® in the
Galaxy™ Implementation Platform maximizes your productivity with its complete solution for RTL synthesis and test. The premier synthesis product,
DC Ultra™, lets you achieve the best quality-of-results and accurately predict post-layout timing, area and power during RTL synthesis, to significantly reduce costly and time-consuming design iterations.
Design Compiler Graphical enables RTL designers to predict, visualize and alleviate wire routing congestion and perform floorplan exploration prior to physical implementation. Additionally, it produces “physical guidance” to
IC Compiler place-and-route for tighter correlation and faster placement runtimes.
DC Explorer, the newest addition to the product line, enables early RTL exploration for accelerating synthesis and place-and-route. The Design Compiler family also includes: the award-winning
Galaxy Test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon;
Power Compiler™, for low power synthesis and optimization; the
Formality® equivalence checker; and the
DesignWare® library with its unequalled variety of synthesizable IP. This best-in-class, production-proven solution is integrated to achieve the industry’s fastest and most predictable RTL-to-GDSII flow.