| Reducing Power with Advanced Synthesis |
Jan 03, 2012 |
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| Enabling early RTL exploration |
DC Explorer enables early RTL exploration to accelerate the development of high-quality RTL and constraints and create a better starting point for synthesis.
Jun 17, 2011 |
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| Bridging the gap between RTL development and design implementation |
The advent of massively integrated, multimillion-instance IC designs is driving the demand for ever-faster design convergence at a time when semiconductor companies are facing unrelenting time-to-market pressures that mandate ever-shorter tapeout schedules. Faster convergence could be achieved by assessing whether design goals can be met earlier in the design cycle, during the RTL development phase, instead of waiting until the implementation phase to discover and correct critical issues.
Mar 28, 2011 |
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| Synopsys debuts DesignWare STAR ECC IP |
Synopsys chose the International Test Conference to announce an expansion of its synthesis-based test technology and announced the availability of its DesignWare STAR ECC (self test and repair error-correcting codes) IP.
Nov 06, 2010 |
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| Synopsys to Expand Synthesis-Based Test Technology |
Synopsys announced plans to expand test technology embedded in Synopsys' RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis while simultaneously minimizing the impact on design goals and project schedules.
Nov 04, 2010 |
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| Are design and test conflicting or symbiotic? |
Although design and test goals may be fundamentally different, are they in direct conflict or are they in fact symbiotic? Read to find out the answer to this question and learn why achieving better design-for-test now requires an approach based in synthesis to enable faster and more predictable results for both design and test.
Oct 08, 2010 |
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| View Point EETimes |
RTL synthesis can accelerate the entire implementation flow
Mar 31, 2010 |
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| Using compression to meet pin-limited test requirements |
This article looks at the industry’s growing need to maintain high scan compression with fewer test pins, and how Wolfson Microelectronics used DFTMAX compression to meet its pin-limited test requirements.
Jan 21, 2010 |
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| Small Delay Defect Testing |
Advances in Synopsys’ TetraMAX ATPG technology have made it possible for semiconductor companies to efficiently target extremely subtle nanometer defects during manufacturing test. This article describes the basic principles behind small delay defect (SDD) ATPG and presents failure statistics on hundreds of thousands of ICs manufactured at STMicroelectronics showing that TetraMAX’s SDD patterns achieve higher defect coverage than standard transition delay patterns.
Jun 01, 2009 |
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| Flexible Analysis is Key to Power Integrity |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008 |
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| Accellera Rolls Power Plan |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008 |
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| Playing it cool |
Power-aware ATPG technology controls thermal and power-rail-droop problems that can damage devices or lead to false failures during production test.
Oct 01, 2008 |
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| Optimizing Compression in Scan-based ATPG DFT Implementations |
Implementing scan compression on-chip provides significant test cost savings, but how much compression is enough? This article introduces a comprehensive economic model unifying test data reduction and test time reduction principles that describes how to determine the optimal compression level for your designs.
Mar 01, 2007 |
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