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Eclypse Low Power Solution
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Absolute Power
Absolute Power is a blog focused on low power design.
Cary Chin
Magic Blue Smoke
Magic Blue Smoke is a blog dedicated to discussing the challenges of low power ASIC Design
Godwin Maben
The Standards Game
Karen Bartleson shares her perspective on what’s going on in the standards arena.
Karen Bartleson
All Synopsys Blogs
LOW POWER VIDEO SERIES
Easiest path to low power design
White Paper
Pain Management in Power Optimization
Absolute Power Blog
Exploration of low power consumer electronics
LOW POWER WEBINARS
Specific topics in low power design & verification
Low Power Design Community
An Inside Look At Transaction-Level Power Modeling
Articles
Considerations for Writing UPF for a Hierarchical Flow
Making IP Tradeoffs For Power
A Shock To The System
Experts At The Table: Verification Nightmares
Have You Really Verified Your Multi-rail, Low Power Design?
Experts At The Table: Low-Power Management and Verification
Low-Power Design Portal Serializes VMM-LP Chapters
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Blogs
Absolute Power
Magic Blue Smoke
The Standards Game
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White Papers
Hybrid Techniques Reduce Dynamic Power Consumption
Pain Management in Power Optimization: Best Practices for Reducing Power, Improving Productivity and Getting SoCs out the Door on Time and on Budget
Testing Low Power Designs with Power Aware Test
Realizing Low Power IC Design: It Starts with the Clock Tree
Synopsys Eclypse Low Power Solution
Eclypse Low Power Solution: Clock Tree Synthesis
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Technical Papers
Low Power Verification Methodology for DSP Core using SVTB
Power and Signal Reliability using HSIMPlus
Automated Design Flow for Reducing Power in a High Performance Synthesizable Processor Core
A predictable approach of reducing clock-tree power using IC Compiler Low-power CTS
Design for Power Gating – and what UPF can, and cannot, do for you!
Leakage Power Optimization: An improved synthesis methodology
Power Rail Noise Minimization for EMC-aware Design
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Presentations
SNUG San Jose 2010: Power Correlation with Silicon - A PrimeTime PX Evaluation
SNUG San Jose 2010: Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster
SNUG San Jose 2010: Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
SNUG San Jose 2010: Clock Power Reduction-Analysis Metrics and Power Reduction Techniques
SNUG Munich 2010: Low Power Verification with MVRC on a Hierarchical UPF Design
SNUG Munich 2010: The Advent of UPF
SNUG France 2010: Ultra Low Power REISC SoC Design Synthesis Flow using DC and UPF-Based Methodology
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Webinars
Low Power Design Made Easy
Approaches for Multi-Voltage Low Power Designs
Bringing Up and Optimizing SW Power Management
Advanced Low Power Synthesis Techniques
Superior Results with the Lynx Design System
Formality Equvialence Checking for Low Power
Power Analysis using PrimeTime PX
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Godwin Maben: Low Power Trends and Methodology
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