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DesignWare Technical Bulletin
DesignWare Technical Bulletin - Q4-11
DesignWare minPower Components
DesignWare Interface IP Goes Virtual
DesignWare Technical Bulletin - Q2-10
Propelled by HDMI, the First 3D Devices Hit the Shelves
DesignWare Mobile Storage Host Controller Core: Handling Timing Requirement for SD3.0 Cards
DesignWare Technical Bulletin - Q1-10
DesignWare Library 2010.03 Release
The DesignWare HDMI 1.4 IP Solutions Revolutionize Home Theatre Multimedia Devices
DesignWare minPower Components 2010.03 Release
Accelerate the Development of Mobile Device with New DesignWare MIPI IP
Synopsys Introduces Industry's First SystemC SuperSpeed USB 3.0 TLM-2.0 Models
New DesignWare OCP Verification IP 3.0 Features
DesignWare Technical Bulletin - Q3-09
Choosing the Right Architecture for Analog-to-Digital Conversion in Wireless Broadband Communications AFEs
Advanced Audio Drivers - The Rising of a New Class of Drivers
New Features for DesignWare DDR3/DDR2 SDRAM Memory Controller IP
DesignWare minPower Components Slash Power in Datapath Circuit
MIPI: Driving Innovation in the Mobile Industry
DesignWare Technical Bulletin - Q2-09
Introducing the Hybrid Architecture for the DesignWare Interconnect Fabric for the AMBA 3 AXI protocol
Synopsys Enables System Design Interoperability with System-Level Catalyst Program
DesignWare DDR3/2 PHY
Beating the Odds on OCP Slave Memory Behavior
Synopsys Releases DesignWare SATA IP for New SATA 6Gb/s Data Transfer Rate
Getting to Market Early With SuperSpeed USB Virtual Platforms
Synopsys Verification IP Alliance
DesignWare Technical Bulletin - Q1-09
What's New in 2008.09 DesignWare Library Datapath and Building Block IP
New VMM-Enabled PCI Express System Example
New Release of DesignWare OCP Verification IP
DesignWare Technical Bulletin - Q3-08
Connecting a Standard SRAM Device to an AMBA 3 AXI Subsystem Using the DesignWare Generic Slave
How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
DesignWare Verification IP Quickstart for AMBA 3 AXI: A New View into Documentation
New Release of DesignWare Verification IP for OCP
DesignWare Technical Bulletin - Q2-08
PCI Express Switch Enumeration Using VMM-Based DesignWare Verification IP
USB 2.0 IP with Link Power Management Extension
Functional Coverage Techniques: Leveraging DesignWare Verification IP and VMM for Efficient Testbenches
Virtualize Your Connectivity IP with DesignWare System-Level Library
DesignWare Technical Bulletin - Q1-08
Synopsys Enhances DesignWare IP for DDR2 and DDR3
Update to Six DesignWare Building Block IP Application Notes
USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Know Your Protocol: A Verification IP Perspective
DDR2/3 SDRAM Controller Options: Protocol or Memory Controller
Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus
Latest DesignWare IP SolvNet Articles
DesignWare Technical Bulletin - Q4-07
New Datapath and Building Block IP in 2007.12 Release of the DesignWare Library
Tradeoffs Between Combinational and Sequential Dividers
Low Power Methodology Demystified: Insights into the LPMM
Understanding the DesignWare USB 2.0 Host Controller's New Feature for OHCI Clocks
PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps
New SolvNet Articles for DesignWare IP for AMBA
DesignWare Technical Bulletin - Q3-07
A Cheat Sheet for the DesignWare Solutions for AMBA IP
A Guide to Understanding the Latest Enhancements for DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric
Synopsys Enhances DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric
Get the Latest Product Information on DesignWare IP Through myDesignWare.com
Extending Open Core Protocol (OCP) Functionality with VMM: Implementing a Slave Memory for Verification IP
Synopsys DesignWare Verification IP Supports PCI Express Gen II and PIPE 1.87 Specifications
DesignWare Technical Bulletin - Q2-07
Overview of 2007.04a Release of DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI
New Download and Installation Process for DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI
DDR2 SNUG Tutorial: DDR2-533 and Beyond with DesignWare Memory Interface IP
Pipelining with DesignWare Building Block IP
Latest Update to DesignWare Documentation and STARS-on-the-web
An Introduction to Synopsys' New SATA AHCI Digital Core Solution
New Release of DesignWare Verification IP for I2C is now available for download
DesignWare Technical Bulletin - Q1-07
2007.03 DesignWare Library Datapath and Building Block IP - DesignWare® Library introduces 19 new Building Block IPs in the 2007.03 release
IP and TCP/UDP Checksum Offload Functionality and its Support in Synopsys' DesignWare Ethernet MAC 10/100/1000 - Universal Core
New SolvNet articles on DW IIP, VIP and DW Cores featuring AMBA, PCI Express and more
Updates to TSMC Nexsys Libraries for the 65-nm and 90-nm Process Technology
DesignWare Verification IP adds support for SystemVerilog and VMM in VCS-MX
DesignWare Verification IP for OCP 2.1 (Open Core Protocol) - Now at Production Release and Ready for Download
DesignWare Introduces Port Monitor Verification IP for the AMBA 3 AXI Protocol
DesignWare Verification IP adds native performance in VCS for Verilog-based Testbenches
DesignWare Technical Bulletin - Q4-06
Using DW_ahb_dmac in an AXI Subsystem
Connecting an AMBA 2.0 AHB Subsystem to an AMBA 3 AXI Subystem
DesignWare Introduces the AMBA 3 AXI to APB3 Bridge and Fabric Synthesizable IP
DesignWare Introduces Bi-Directional Command Support in Interconnect Fabric for AMBA 3 AXI
Performance of Different Multipliers in the DesignWare Building Block IP
DesignWare Technical Bulletin - Q3-06
coreTools 2006.03 is now available
What's New in 2006.06 DesignWare Library Datapath and Building Block IP
New Floating Point Components in DesignWare Library
XGXS-PCS IP - PCS for 10G Ethernet eXtender Sublayer
DesignWare Technical Bulletin - Q2-06
Deciding on FIFO Sizes When Implementing DW Digital Cores
Article
Semiconductor IP: Enabling SoC
Success Story
Siglead Achieves First-Pass Silicon Success with DesignWare SATA, DDR and DesignWare Library
WEBINAR - ON DEMAND
Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
Success Story
PLX First to Market with PCI Express Gen 3 Switch using DesignWare Embedded Memory IP
News
Synopsys Unveils Industry’s First Complete Audio IP Subsystem
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AMD Selects Synopsys as a Verification IP Partner
Synopsys Unveils Industry's First Complete Audio IP Subsystem
Synopsys Extends Leadership in Storage Standards Verification IP with NVM Express
GUC and Synopsys Achieve Design Milestone
Synopsys Introduces Industry's First 28-nm Multi-Gear MIPI Alliance M-PHY IP....
Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs
Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC....
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All Synopsys News
Articles
New Electronics Outlook 2012: Semiconductor IP: enabling SoC
Electronic Design: ADC Performance: What's Jitter Got To Do With It?
Delivering Great Audio with an SoC-Ready, IP Subsystem Solution
EETimes Audio Design: Integrating audio codecs in next-generation SoCs for smartphones and tablets
ChipEstimate.com: Integrating Analog IP in 28-nm Processes
ChipEstimate.com: When Once Is Not Enough - Technology Choices for Few- and Multiple-Time Programmable Non-Volatile Memory
Synopsys Insight: Next-Generation Low-Power Data Converters for High-Performance Communication Applications
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Blogs
The Sound Room
Configurable Thoughts
USB IP Blog: To USB or Not to USB
The Eyes Have it: A Mixed-Signal IP Blog
On the Move: MIPI IP Blog
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Success Stories
Siglead Achieves First-Pass Silicon Success with DesignWare SATA, DDR and DesignWare Library
PLX First to Market with PCI Express Gen 3 Switch using DesignWare Embedded Memory IP
Synopsys and Analog Devices - Analog Devices Achieves Silicon Success for Multiple ICs Using DesignWare Non-Volatile Memory IP
Synopsys and DisplayLink - DisplayLink Achieves First-Pass Silicon Success with DesignWare SuperSpeed USB 3.0 IP
Synopsys and Global Unichip - GUC Meets Aggressive Time-to-Market Deadlines for Multiple Mobile Multimedia SoCs using DesignWare IP
Wilocity Teams with Synopsys - Synopsys Professional Services Integrates DesignWare IP for 65nm Wireless PCI Express Design
Verayo Achieves First-Pass Silicon Success for RFID Security IC with DesignWare AEON NVM IP
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White Papers
High-End Audio Made Easy: The Software Story
Audio Subsystems for Efficient SoC Integration
Unleash the Performance Benefits of Sigma-Delta ADCs into Your SoC: IP supports cellular communications, sensors and measurement markets
Protect Your Electronic Wallet Against Hackers: Securing Critical Data in Consumer and Multimedia Mobile Devices with NFC technology using Non-volatile Memory IP
Shrinking SoC Design Cycles Using DesignWare Intellectual Property
Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP
Reality Check: A Guide to Understanding Optimized Processor Cores
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Webinars
Audio IP Subsystems Made Easy
Effect of Jitter on Data Converters
Bringing Embedded MTP NVM IP to Advanced Process Nodes
ARC Android - Making Android Affordable Anywhere
Reliability & Qualification of MTP NVM IP Webinar-China
DesignWare ARC EM 32-bit Processor Family
Designing AMBA-based SoCs with a PCI Express Interface
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Videos
Synopsys Demonstrates DesignWare® HDMI Receiver IP Solution with Fast Switching
Featured Analog Video: Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution
Featured USB Video: DisplayLink demonstrates chip with Synopsys USB 3.0 & HDMI IP
Industry’s First Complete Audio IP Subsystem
Synopsys DesignWare SATA 6 Gb/s AHCI Host Controller and PHY
Synopsys DesignWare PCI Express 3.0 with LeCroy Protocol Test Suite
Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair
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