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Synopsys’ DesignWare® Logic Libraries portfolio includes the SiWare® Logic and ASAP Logic cell libraries. The SiWare Logic product line includes yield-optimized standard cells for a wide array of design applications from 65 nm to 28 nm process nodes with multiple threshold process variants. The ASAP Logic product line consists of metal programmable and standard cell libraries designed to meet the highest quality and performance standards for 180 nm to 90 nm process nodes.
- SiWare Logic
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Yield-optimized standard cells for 65 nm to 28 nm process nodes | more |
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The SiWare-Logic libraries are offered using three separate architectures to optimize circuits for High-Density, Ultra-High-Density or High-Speed for area, speed, and power tradeoffs |
- ASAP Logic
| Application-optimized cell libraries for 90 nm to 180 nm process nodes | more |
| Standard Cell Libraries |
Depending on design objectives select from High-Density, Ultra-High-Density and Ultra-Low-Power Standard Cell architectures |
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| Metal Programmable Libraries |
The metal programmable cell libraries, available in High-Speed and High-Density architectures, are most beneficial to designers who are looking for a foundation for low-cost mask designs |
| | As an integral part of the SoC design and manufacturing ecosystem, Synopsys collaborates with foundry partners to offer comprehensive solutions for a wide spectrum of technology nodes |
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