Monday, March 28, 2011
Tuesday, March 29, 2011
Wednesday, March 30, 2011 Monday, March 28, 2011
| Time | Description | | 7:30-9:00 | Registration and Breakfast | | 9:00-10:30 | | | 10:30-11:00 | Break | | | IC Design - Implementation A | IC Design -
Custom Design | IC Design - Signoff | IC Verification | FPGA | AMS Verification | | 11:00-12:30 | MA1 User
DFM/Routing | MA2 Tutorial
Synopsys Custom Design Solution | MA3 Tutorial
Analyzing the Effectiveness of Multi-Voltage Power Saving Techniques with PT-PX | MA4 User
Constraints and Design Partitioning | MA5 Vision
Accelerating the ‘Programmable Imperative’ – From Programmable Logic to Programmable Platforms | MA6 Tutorials
HSPICE | | 12:30-1:45 | Lunch | | | 1:45-3:15 | MB1 Tutorials
IC Compiler | MB2 User & Tutorial
Custom Designer, PDKs and StarRC | MB3 User
PrimeTimePX | MB4 User
SystemVerilog and VMM | MB5 Tutorial
FPGA Flows from Top-Down to Bottom-Up | MB6 User
MOSFET & HSPICE | | 3:15-3:35 | Break | | 3:35-5:05 | MC1 User & Panel
Architecture Feasibility & Lynx Design System | MC2 Tutorial
Addressing Physical Verification Challenges at 28nm and Below with IC Validator | MC3 Vision
PrimeTime HyperScale Technology | MC4 User
Verification Methodology & Magellan | MC5 User
FPGA Design | MC6 User
HSPICE & CustomSim-XA | | 4:30-7:30 | |
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Tuesday, March 29, 2011
| Time | Description | | 7:30-9:00 | Registration and Breakfast | | 9:00-10:00 | | | 10:00-10:15 | Break |  | IC Design - Implementation A | IC Design - Implementation B | IC Design - Signoff | IC Verification | FPGA | Compute and Design Infrastructure | System-Level Design | | 10:15-11:45 | TA1 Vision
IC Physical Design – Yesterday, Today and Tomorrow | TA2 Tutorial
DC 2010.12 Update | TA3 Tutorial
Faster Multi-Scenario ECO Fixing in PrimeTime | TA4 User
VCS Compile and Runtime Improvements | TA5 Tutorial
Partitioning and Reconnecting: A Key Prototyping Expertise | | TA7 Tutorial
Scaling High-Level Synthesis for Complex Image and Video Processing Designs | | 11:45-1:00 | Lunch | | 1:00-2:30 | TB1 User
IC Compiler & Hierarchical Design | TB2 Tutorial Eliminating Late-Stage Manual Fixes with In-Design Physical Verification | TB3 User PrimeTime DMSA, ECO and AOCV | TB4 Tutorial
VCS Productivity Tools and Technologies that Help Reduce the Ever-Growing Verification Cycle | TB5 User
FPGA Prototyping | TB6 Tutorials License Infrastructure Best Practices | TB7 Tutorial Using Embedded Software to Accelerate Verification | | 2:30-2:50 | Break | | 2:50-4:50 | TC1 User
Low Power & Timing Closure | TC2 Tutorial
IC Compiler and Timing Closure | TC3 User & Tutorial
Galaxy Constraint Analyzer | TC4 Tutorial & User
Low Power Verification | TC5 Tutorial
Enhancing an IP Validation Environment Utilizing FPGA-Based Prototyping | TC6 Tutorials
Computing Compute Resource Strategies and GPU Applications | TC7 Tutorial
Replacing Fixed Hardware Blocks with Custom Processors | | 4:15-6:30 | SNUGtoberfest |
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Wednesday, March 30, 2011
| Time | Description | | 7:30-9:00 | Registration and Breakfast | | 9:00-10:00 | | | 10:00-10:15 | Break | | | IC Design -
Implementation A | IC Design - Test | IC Design - Signoff | IC Verification | IPSummit at SNUG | | 10:15-11:45 | WA1 Tutorial
IC Compiler, Fast Hierarchical Design Exploration, Planning, Block Implementation and Top-level Closure | WA2 User
Test | WA3 Tutorial
ESP Power Intent Verification | WA4 Tutorial
New Levels of Verification IP Productivity | WA5 Tutorial
Integrating MIPI Interfaces for Camera and Display Peripherals in SoCs
(with case study by OSI) | WA6 Tutorial
How Chip Designers Can Benefit From Low-Power Embedded Memory Design Techniques | WA7 Tutorial
USB 3.0 IP: The Path from Concept to Certified Products | | 11:45-12:45 | Lunch | | 12:45-2:15 | WB1 Tutorial
New Multi-Voltage Power Optimization Techniques to Address Power Reduction During Design Implementation | WB2 Tutorial DFTMAX Compression, TetraMAX ATPG, and the STAR Memory System Updates | WB3 User & Tutorial
NanoTime | WB4 Tutorial
New Advancements in Methodology to Improve Verification Turn-Around-Time | WB5 Tutorial
Reducing Static Power Consumption in Advanced SoC Designs Using Long and Multi-Channel Logic Libraries | WB6 Tutorial
Configuring DesignWare ARC Processors To Your Embedded or Host SoC Application | WB7 Tutorial
How To Avoid Design Pitfalls and Ensure a Successful DDR PHY Implementation | | 2:15-3:00 | Break and Awards Presentations | | 3:00-4:30 | WC1 Tutorial
IC Compiler Design Planning with Template-Based Power Network Synthesiss | WC2 Panel How Much Test Coverage is Enough? | WC3 Tutorial
StarRC 2010.12: Faster Extraction for 28-nm Designs | WC4 White Paper
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks | WC5 Tutorial
Designing Mobile Multimedia SoCs with Low-Power, High-Performance IP Solutions | WC6 Tutorial
Implementing Low-Power Designs with DesignWare minPower Components | WC7 Tutorial
Addressing the Challenges of Designing an AMBA-based SoC with a PCI Express Interface |
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