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SNUG France 

Grenoble World Trade Center 
Grenoble, France
14 June 2012

SNUG France is your opportunity to learn, share and engage with your fellow Synopsys technology users. In addition to an exceptional technical program that will give you practical information you can apply to your current project or use to jump-start your next design, SNUG also offers plenty of opportunities to share experiences, network with other users and meet with Synopsys experts to learn about the newest products and preview future technology direction.

 

 
Please submit your proposal by 7 Feb 2012 to be considered for a SNUG presentation spot.

Required Templates
DOCUser Paper Template PPTUser Presentation Template

Dates to Remember
    5 December 2011 Call for papers opens
     7 February 2012 Call for papers closes
    10 February 2012 Preliminary acceptance notification
    5 March 2012 Draft paper due
    26 March 2012 Final paper due
    2 April 2012 Final acceptance notification and presentation spots awarded
    11 May 2012 Draft slides due
    31 May 2012 Final slides due
    14 June 2012 SNUG France 2012

SNUG France
23 June 2011

Conference Schedule
SNUG France attracted Synopsys users from companies across Europe on 23 June 2011. Users exchange ideas with peers and product experts while attending technical presentations across 8 different EDA technologies. 

SNUG France Proceedings
Check out the proceedings library to locate user papers or tutorials that contain solutions you can apply to your own design challenges.

1st Place - Best Paper Improve Verification Coverage of an Asynchronous Microcontroller with System Verilog - HSIM Co-simulation
Bertrand Folco [Tiempo France]
PaperPresentation

2nd Place - Best Paper Efficient Standard Cell Characterization for GLOBALFOUNDRIES 28nm Technologies using a Star-RC and Liberty-NCX-based Flow
Robert Siegmund, Ben Gullette, Andre Schulze [GLOBALFOUNDRIES]
PaperPresentation

3rd Place - Best Paper Reconfigurable Wrapper Test Access Mechanism (TAM) in a Core Based DFT Strategy to Save Interconnect Test Time
Isabelle Delbaere, Caroline Carin and Christophe Eychenne [ST-Ericsson]
PaperPresentation

Technical Committee Award Honorable Mention UPF Power State Table Verification Methodology using MVSIM
Christophe Clavel [ST-Ericsson]
PaperPresentation

Technical Committee Award ICC-Custom Designer Link to Improve the Product Development Cycle Time!
Christelle Leherpeur [ST Microelectronics France]
PaperPresentation

ProceedingsDownload 2011 proceedings
PAPERS (26 MB) PRESENTATIONS (24 MB) TUTORIALS (79 MB)
SNUG thanks the members of the Technical Committee who volunteer their time and expertise to ensure SNUG’s technical quality, local perspective and value to the users of Synopsys tools and technology.

User Technical Chairs
Frank Poppen, OFFIS Institute for Information Technology
SNUG Europe Technical Chair

Mike Bartley, Test and Verification Solutions Ltd
SNUG UK Technical Chair

Patrick Richier, ST-Ericsson
SNUG France Technical Chair

Members
Alessandro Valerio, STMicroelectronics
Alkiviadis Boulos, Jaguar & Land Rover
Claus Kuntzsch, Texas Instruments
Christophe Scarabello, Tiempo SAS
David Tester, Structured Custom Ltd.
Evagelia Diamantakou, Intracom
Franco Cesari, STMicroelectronics
Herbert Preuthen, LSI Corporation
Herbert Taucher, Siemens AG Austria
Jerome Bombal, Texas Instruments
Justin Mitchell, BBC
Karsten Matt, GLOBALFOUNDRIES
Laurent Besson, ST-Ericsson		 Majid Ghameshlu, Siemens AG Austria
Marcus Sarnoch, Independent
Norbert Schuhmann, Fraunhofer Institute for IC
Paul Fugger, Infineon Technologies
Pierluigi Daglio, STMicroelectronics
Ralf Leuchter, Infineon Technologies AG
Richard Illman, Dialog Semiconductor
Shalom Bresticker, Intel
Stefano Pucillo, STMicroelectronics
Stuart Vernon, Imagination Technologies
Tiana Rahaga, EASII IC
Tobias Thiel, Freescale Semiconductor
Wolfgang Roessel, Alcatel


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